MPC2002SG50中文资料摩托罗拉数据手册PDF规格书

The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance,256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x72 bits in a 136 pin dual read out single inline memory module (DIMM). The module uses four of Motorola’s MCM67M518 or MCM67M618 BiCMOS BurstRAMs.

• PowerPC–style Burst Counter on Board

• Dual Readout SIMM for Circuit Density

• Single 5 V ±5 Power Supply

• All Inputs and Outputs are TTL Compatible

• Three State Outputs

• Byte Parity

• Byte Write Capability

• Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz

• Decoupling Capacitors for each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• I/Os are 3.3 V Compatible