MPC2001SG12中文资料摩托罗拉数据手册PDF规格书

The MPC2001 is designed to provide asynchronous 256KB L2 cache for the PowerPC 60x processors. The module is configured as 32K x 64 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses eight of Motorola’s MCM6206 CMOS RAMs.

Eight write enables are provided for byte write control.

The cache is designed to interface with the PowerPC 60x bus and requires external tag. PD0 – PD2 are reserved for density and speed identification.

The cache is plug and pin compatible with Motorola’s MPC2002 and MPC2003 BurstRAM™ synchronous cache modules.

• Dual Readout SIMM (DIMM) for Circuit Density

• Single 5 V ± 5 Power Supply

• All Inputs and Outputs are TTL Compatible

• Three State Outputs

• Byte Write Capability

• Decoupling Capacitors for each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• Fast SRAM Access Times 12 ns, 15 ns

• Low Cost Asynchronous Solution for MPC105 PCI Bridge/Memory Controller Chip