MM54HC195J中文资料4-Bit Parallel Shift Register数据手册TI规格书

描述 Description

General Description
The MM54HC195/MM74HC195 is a high speed 4-bit SHIFT REGISTER utilizes advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads at LS type speeds.
This shift register features parallel inputs, parallel outputs, JK serial inputs, SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in two modes: PARALLEL LOAD; SHIFT from QA towards QD.
Parallel loading is accomplished by applying the four bits of data, and taking the SHIFT/LOAD control input low. The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the SHIFT/LOAD control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table.
The 54HC/74HC logic family is functionally as well as pin out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

特性 Features

■ Typical operating frequency: 45 MHz
■ Typical propagation delay: 16 ns (clock to Q)
■ Wide operating supply voltage range: 2–6V
■ Low input current: 1 μA maximum
■ Low quiescent current: 80 μA maximum (74HC Series)
■ Fanout of 10 LS-TTL loads