MC92501中文资料摩托罗拉数据手册PDF规格书

The MC92501 is an Asynchronous Transfer Mode (ATM) Cell Processor layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and UTOPIA Level 1-compliant switch interface (see Figure 1). It integrates address translation, UPC/NPC, OAM, and statistical functions into a single semiconductor device.

New Features in the MC92501

• Implements ATM Layer functions for Broadband ISDN according to ANSI recommendations, ATM Forum UNI 4.0 and TM 4.0 Specifications, ITU recommendations, and Bellcore recommendations.

• Provides ABR Relative Rate marking and EFCI marking according to TM 4.0

• Select Discard CLP = 1 (or CLP = 0 + 1) Flow on selected connections

• UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface

• Supports both Partial Packet Discard (PPD) and Early Packet Discard (EPD)

• Change ABR RM Cell priority

• Supports CLP transparency

• Unidirectional (Ingress or Egress) UPC or NPC

Standard ATMC Features in the MC92500 Family

• Full duplex operation at data rates up to 155 Mbps

• Performs internal VPI and VCI address compression for up to 64 K VCs

• CLP-Aware peak, average, and burst-length policing with programmable Tag/Drop action per policer

• Supports up to 16 physical links unsing dedicated Ingress/Egress multiPHY control signals

• Each physical link can be configured as either a UNI or NNI port

• Supports multicast, multiport address translation

• Maintains both virtual connection and physical link counters on both Ingress and Egress cell flows

• Provides a flexible 32-bit external memory port for context management

• Automated AIS, RDI, CC, and loopback functions with performance monitoring block test on all 64 K connections

• Programmable 32-bit microprocessor interface supporting Big-Endian or Little Endian bus formats

• Unidirectional (Ingress only) UPC or NPC design with up to four leaky buckets per connection

• Supports a programmable number of additional switch overhead parameters allowing adaptiation to any switch routing header format

• Provides per-link cell counters in both directions