MC92460EC/D中文资料恩XP数据手册PDF规格书

特性 Features

The following is an overview of the MC92460 feature set:

• Channels

— 40 full-duplex HDLC channels

— Programmable channel assignment (any logical channel to any signal)

— Each channel has a default of 64 buffer descriptors (Rx and Tx) but the number of buffer

descriptors per channel is configurable

• Controllers

— Maximum throughput of 1919 Mbps; individual controllers operate up to 66.7 Mbps

— All communication controllers operate asynchronously

— Programmable frame size (maximum 65,535 bytes)

— Transparent memory access with internal memory controller

• 60x Bus

— MC92460 directly connects with a 64-bit data and 32-bit address 60x bus

— Supports 66.7 MHz 60x bus speed, with aggregate bandwidth of up to 1919 Mbps depending

on the type of main memory used

— Up to four MC92460’s may be connected in parallel on the 60x bus

— Bus supports multiple master design

• Communication Buffers

— Data Buffer

– 256 Kbits on-chip memory for data buffers

– 256 Kbit communication buffer can store up to 819 bytes per frame.

– 80 channel virtual DMA functionality executes between off-chip memory and the

communication buffer

— BD Buffer

– 32 Kbyte on-chip dual-port RAM for buffer descriptors

– A total of 4096 buffer descriptors (2048 TxBD and 2048 RxBD)

• JTAG Support

— Supports the IEEE1149.1 JTAG controller standard

• Power and Clocks

— Supports single-beat and burst accesses

— On-chip PLL for baud rate generator (maximum of 66.7 MHz)

— Separate power supplies for core internal logic (1.8V) and for I/O (3.3V)

• Package

— 480 pin TPGA, 1.27 mm pitch