QUAD 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS HIGH-PERFORMANCE SILICON-GATE CMOS

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High–Performance Silicon–Gate CMOS TheMC54/74HC132A is identical in pinout to the LS132. The device inputsare compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. TheHC132A can be used to

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OCTAL 3-STATE INVERTING TRANSPARENT LATCH HIGH-PERFORMANCE SILICON-GATE CMOS

Octal 3-State Inverting Transparent Latch High–Performance Silicon–Gate CMOS The MC54/74HC533A is identical in pinout to the LS533. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparen

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Quad 3-State Noninverting Buffers

The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3–state memory address

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High–Performance Silicon–Gate CMOS

• Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Comp

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8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT REGISTER

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8-BIT SERIAL OR PARALLEL-INPUT/SERIAL-OUTPUT SHIFT REGISTER

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High?밣erformance Silicon?밎ate CMOS

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High?밣erformance Silicon?밎ate CMOS

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High?밣erformance Silicon?밎ate CMOS

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High?밣erformance Silicon?밎ate CMOS

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