첨2/4,첨4/6 Clock Generation Chip

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. • 50ps Output-to-Output S

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Motorola

摩托罗拉

첨2/4,첨4/6 Clock Generation Chip

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but is specified for operation at the standard 100K ECL voltage supply. • 50ps Output-to-Output S

文件：127.04 Kbytes 页数：4 Pages

Motorola

摩托罗拉

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

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3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

3.3/5VECL Differential Phase?묯requency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

文件：108.5 Kbytes 页数：6 Pages

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Phase-Frequency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

文件：72.39 Kbytes 页数：3 Pages

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3.3/5VECL Differential Phase?묯requency Detector

Description The MC100LVEL40 is a three state phase frequency−detector intended for phase−locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rat

文件：108.5 Kbytes 页数：6 Pages

ONSEMI

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Differential Clock D Flip-Flop

Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applica

文件：82.27 Kbytes 页数：3 Pages

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