3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

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3.3V ECL 첨2/4, 첨4/6 Clock Generation Chip

Description The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differ

文件：120.76 Kbytes 页数：6 Pages

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安森美半导体

3.3V ECL Clock Generation Chip

文件：160.08 Kbytes 页数：6 Pages

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Package：20-SOIC（0.295"，7.50mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN ECL 2:4 4/6 20SOIC

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