3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes 页数：11 Pages

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ECL D Flip-Flop with Reset and Differential Clock

文件：156.53 Kbytes 页数：11 Pages

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Package：8-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 1BIT 8SOIC

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安森美半导体

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

文件：76.11 Kbytes 页数：8 Pages

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安森美半导体