MC100E016

8-BIT SYNCHRONOUS BINARY UP COUNTER

Description TheMC10E/100E016isahigh−speedsynchronous,presettable,cascadable8−bitbinarycounter.ArchitectureandoperationarethesameastheMC10H016intheMECL10H™family,extendedto8−bits,asshowninthelogicsymbol. Features •700MHzMin.CountFrequency •1000psCLK

MC100E101

QUAD 4-INPUT OR/NOR GATE

TheMC10E/100E101isaquad4-inputOR/NORgate. •500psMax.PropagationDelay •Extended100EVEERangeof–4.2Vto–5.46V •75kΩInputPulldownResistors

MC100E101

5V ECL Quad 4짯Input OR/NOR Gate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

MC100E101FN

5V ECL Quad 4짯Input OR/NOR Gate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

MC100E101FNR2

5V ECL Quad 4짯Input OR/NOR Gate

Description TheMC10E/100E101isaquad4-inputOR/NORgate. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange: VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange: VCC=0VwithVEE=−4.2Vto−5.7

MC100E104

QUINT 2-INPUT AND/NAND GATE

Description TheMC10E/100E104isaquint2-inputAND/NANDgate.ThefunctionoutputFistheORofallfiveANDgateoutputs,whileFistheNOR.TheQoutputsneednotbeterminatedifonlytheFoutputsaretobeused.The100Seriescontainstemperaturecompensation. Features •600psMax.P

MC100E107

QUINT 2-INPUT XOR/XNOR GATE

Description TheMC10E/100E107isaquint2-inputXOR/XNORgate.ThefunctionoutputFistheORofallfiveXORoutputs,whileFistheNOR.TheQoutputsneednotbeterminatedifonlytheFoutputsaretobeused. The100Seriescontainstemperaturecompensation. Features •600psMaximumPr

MC100E111

1:9 DIFFERENTIAL CLOCK DRIVER

Description TheMC10E/100E111isalowskew1-to-9differentialdriver,designedwithclockdistributioninmind.Itacceptsonesignalinput,whichcanbeeitherdifferentialorelsesingle-endediftheVBBoutputisused.Thesignalisfannedoutto9identicaldifferentialoutputs.Anenablei

MC100E112

QUAD DRIVER

Description TheMC10E/100E112isaquaddriverwithtwopairsofOR/NORoutputsfromeachgate,andacommon,bufferedenableinput.UsingthedatainputsthedevicecanserveasanECLmemoryaddressfan-outdriver.Usingjusttheenableinput,thedeviceservesasaclockdriver,althoughtheM

MC100E116

QUINT DIFFERENTIAL LINE RECEIVER

Description TheMC10E/100E116isaquintdifferentiallinereceiverwithemitter-followeroutputs.ForapplicationswhichrequirebandwidthsgreaterthanthatoftheE116,theE416devicemaybeofinterest. ActivecurrentsourcesplusadeepcollectorfeatureoftheMOSAICIIIprocessprovidet

MC100E122

9-BIT BUFFER

Description TheMC10E/100E122isa9-bitbuffer.Thedevicecontainsninenon-invertingbuffergates. The100Seriescontainstemperaturecompensation. Features •500psMax.PropagationDelay •PECLModeOperatingRange:VCC=4.2Vto5.7VwithVEE=0V •NECLModeOperatingRange:VCC=

MC100E131

4-BIT D FLIP-FLOP

Description TheMC10E/100E131isaquadmaster-slaveD-typeflip-flopwithdifferentialoutputs.Eachflip-flopmaybeclockedseparatelybyholdingCommonClock(CC)LOWandusingtheClockEnable(CE)inputsforclocking.CommonclockingisachievedbyholdingtheCEinputsLOWandusingCCto

MC100E136

6-BIT UNIVERSAL UP/DOWN COUNTER

Description TheMC10E/100E136isa6-bitsynchronous,presettable,cascadableuniversalcounter.Thedevicegeneratesalook-ahead-carryoutputandacceptsalook-ahead-carryinput.ThesetwofeaturesallowforthecascadingofmultipleE136’sforwiderbitwidthcountersthatoperateatverynea

MC100E137

8-BIT RIPPLE COUNTER

Description TheMC10E/100E137isaveryhighspeedbinaryripplecounter.ThetwoleastsignificantbitsweredesignedwithveryfastedgerateswhilethemoresignificantbitsmaintainstandardECLinPS™outputedgerates.Thisallowsthecountertooperateatveryhighfrequencieswhilemaintain

MC100E141

8-BIT SHIFT REGISTER

Description TheMC10E/100E141isan8-bitfull-functionshiftregister.TheE141performsserial/parallelinandserial/parallelout,shiftingineitherdirection.TheeightinputsD0−D7acceptparallelinputdata,whileDL/DRacceptserialinputdataforleft/rightshifting.TheQnoutputsdo

MC100E142

9-BIT SHIFT REGISTER

Description TheMC10E/100E142isa9-bitshiftregister,designedwithbyte-parityapplicationsinmind.TheE142performsserial/parallelinandserial/parallelout,shiftinginonedirection.ThenineinputsD0−D8acceptparallelinputdata,whileS-INacceptsserialinputdata.TheQnoutput

MC100E143

9-BIT HOLD REGISTER

Description TheMC10E/100E143isa9-bitholdingregister,designedwithbyte-parityapplicationsinmind.TheE143holdscurrentdataorloadsnewdata,withthenineinputsD0−D8acceptingparallelinputdata. TheSEL(Select)inputpinisusedtoswitchbetweenthetwomodesofoperation−

MC100E150

6-BIT D LATCH

Description TheMC10E/100E150containssixD-typelatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparentandinputdatatransitionspropagatethroughtotheoutput.AlogicHIGHoneitherLEN1orLEN2(orboth)latchesthedata.TheMasterReset

MC100E151

6-BIT D REGISTER

Description TheMC10E/100E151contains6D-type,edge-triggered,master-slaveflip-flopswithdifferentialoutputs.DataentersthemasterwhenbothCLK1andCLK2areLOW,andistransferredtotheslavewhenCLK1orCLK2(orboth)goHIGH.TheasynchronousMasterReset(MR)makesallQoutputsg

MC100E154

5-BIT 2:1 MUX-LATCH

Description TheMC10E/100E154containsfive2:1multiplexersfollowedbytransparentlatcheswithdifferentialoutputs.WhenbothLatchEnables(LEN1,LEN2)areLOW,thelatchistransparent,andoutputdataiscontrolledbythemultiplexerselectcontrol,SEL.AlogicHIGHoneitherLEN1orLEN2