Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

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用于高速时钟分配系统的延时线

MAX3620系列高性能无源延时线适用于QDR/QDRII同步存储器系统。这些延时线支持高速收发器逻辑(HSTL)源端接，接收器无端接负载传输，可实现0.75ns、1.00ns、1.25ns和1.50ns的精确延时，产生四分之一时钟相位。MAX3620提供小型3mm x 3mm封装，含两个等长，可差分驱动或单端驱动的延时线。 \n• 支持HSTL源端接传输线 \n• 全部无源设计 \n• 与100Ω差分和50Ω单端传输线兼容 \n• 小型3mm x 3mm封装;

ADI

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Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Package：6-WDFN 裸露焊盘；包装：卷带（TR） 功能：多重 类别：集成电路（IC） 延迟线 描述：IC DELAY LINE 1NS 6TDFN

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Package：6-WDFN 裸露焊盘；包装：卷带（TR） 功能：多重 类别：集成电路（IC） 延迟线 描述：IC DELAY LINE 1.25NS 6TDFN

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