Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信

Delay Lines for High-Speed Clock Distribution Systems

General Description The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate

文件：159.71 Kbytes 页数：6 Pages

Maxim

美信