M54HCT138F1R中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combinedwithtrue CMOSlowpower consumption.

■ HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V

■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C

■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

■ BALANCED PROPAGATION DELAYS tPLH = tPHL

■ SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL

■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX)

■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS138