M54HCT137中文资料意法半导体数据手册PDF规格书

DESCRIPTION

TheM54/74HCT137 isahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gateC2MOStechnology. Ithas the samehigh speedperformanceofLSTTL combined withtrueCMOSlowpower consumption.

■ HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V

■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C

■ COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX)

■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

■ SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.)

■ BALANCED PROPAGATION DELAYS tPLH = tPHL

■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS137