256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising

文件：644.95 Kbytes 页数：41 Pages

ELPIDA

尔必达

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit, M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit, M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK

文件：824.58 Kbytes 页数：37 Pages

Mitsubishi

三菱电机

256M Double Data Rate Synchronous DRAM

MITSUBISHI

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION\nM2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit,\nM2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit,\nM2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit,\ndouble data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. - Vdd=Vddq=2.5V+0.2V\n- Double data rate architecture; two data transfers per clock cycle\n- Bidirectional, data strobe (DQS) is transmitted/received with data\n- Differential clock inputs (CLK and /CLK)\n- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS\n- Commands entered on ea;

MITSUBISHI

三菱电机