256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and

文件：300.44 Kbytes 页数：36 Pages

MITSUBISHI

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and

文件：300.44 Kbytes 页数：36 Pages

MITSUBISHI

三菱电机

256M Double Data Rate Synchronous DRAM

DESCRIPTION M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and

文件：300.44 Kbytes 页数：36 Pages

MITSUBISHI

三菱电机

256M Double Data Rate Synchronous DRAM

MITSUBISHI

三菱电机