丝印：LV8；Package：UJ-5；20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator

GENERAL DESCRIPTION The ADP7118 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits operating from 20 V down to 1.2

文件：915.43 Kbytes 页数：24 Pages

AD

亚德诺

丝印：LV8245Q；Package：VQFN；SN74LV8T245-Q1 Automotive 1.65 V to 5 V, Octal Bus Transceiver With 3-State Outputs and Logic Level Shifter

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • Wide operating range of 1.8 V to 5.5 V • Available in wettable flank QFN (WRKS) package • Single

文件：1.49848 Mbytes 页数：26 Pages

TI

德州仪器

丝印：LV8245Q；Package：VQFN；SN74LV8T245-Q1 Automotive 1.65 V to 5 V, Octal Bus Transceiver With 3-State Outputs and Logic Level Shifter

1 Features • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: –40°C to +125°C, TA – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C6 • Wide operating range of 1.8 V to 5.5 V • Available in wettable flank QFN (WRKS) package • Single

文件：1.6747 Mbytes 页数：31 Pages

TI

德州仪器

丝印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different packages 0.75 ns • Max propagation delay of 3.8 ns • Operating voltage of 1.5 V to 2.5 V on Bank A • Operating voltage of 1.5 V to 2.5 V on Banks B and C • Advanced, low power, CM

文件：479.97 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different packages 0.75 ns • Max propagation delay of 3.8 ns • Operating voltage of 1.5 V to 2.5 V on Bank A • Operating voltage of 1.5 V to 2.5 V on Banks B and C • Advanced, low power, CM

文件：479.97 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different packages 0.75 ns • Max propagation delay of 3.8 ns • Operating voltage of 1.5 V to 2.5 V on Bank A • Operating voltage of 1.5 V to 2.5 V on Banks B and C • Advanced, low power, CM

文件：479.97 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LV810RILF；Package：QSOP；BUFFER/CLOCK DRIVER

Features • Packaged in 20-pin QSOP/SSOP • Split 1:10 fanout Buffer • Maximum skew between outputs of different packages 0.75 ns • Max propagation delay of 3.8 ns • Operating voltage of 1.5 V to 2.5 V on Bank A • Operating voltage of 1.5 V to 2.5 V on Banks B and C • Advanced, low power, CM

文件：479.97 Kbytes 页数：15 Pages

RENESAS

瑞萨

丝印：LV8968BB；Package：SPQFP48K；Multi-purpose Three-Phase BLDC Predriver

Overview The LV8968BB is a multi−purpose three−phase BLDC predriver for automotive applications and developed in compliance with ISO 26262. This 3−phase peripheral predriver offers a BEMF (Back ElectroMotive Force) output and the wide operating voltage range and AEC−Q100 qualification make th

文件：382.67 Kbytes 页数：35 Pages

ONSEMI

安森美半导体

丝印：LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 页数：20 Pages

TI

德州仪器

丝印：LV8151；Package：TVSOP；10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

2-V to 5.5-V VCC Operation Max tpd of 15 ns at 5 V Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time Polarity Control for Y Outputs Selects True or Complementary Logic Typical VOLP (Output Ground Bounce) 2.3 V

文件：569.4 Kbytes 页数：20 Pages

TI

德州仪器