LPC43S67JET256数据手册恩XP中文资料规格书

描述 Description

The LPC43S6x are Arm Cortex-M4 based microcontrollers for embedded applications whichinclude an Arm Cortex-M0 coprocessor and an Arm Cortex-M0 subsystem for managingperipherals, up to 1 MB of flash and 154 kB of on-chip SRAM, 16 kB of EEPROM memory, aquad SPI Flash Interface (SPIFI), advanced configurable peripherals such as theSCTimer/PWM and the Serial General Purpose I/O (SGPIO) interface, security features withAES engine, two High-speed USB controllers, Ethernet, LCD, an external memorycontroller, and multiple digital and analog peripherals. The LPC43S6x operate at CPUfrequencies of up to 204 MHz.
The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low powerconsumption, enhanced debug features, and a high level of support block integration. TheArmCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated into the core.
The LPC43S6x include an application Arm Cortex-M0 coprocessor and a second Arm Cortex-M0subsystem for managing the SGPIO and SPI peripherals.The Arm Cortex-M0 coprocessor is anenergy-efficient and easy-to-use 32-bit core which is upward code- and tool-compatiblewith the Cortex-M4 core. The Cortex-M0 coprocessor, designed as a replacement forexisting 8/16-bit microcontrollers, offers up to 204 MHz performance with a simpleinstruction set and reduced code size. The Cortex-M0 coprocessor hardware multiply isimplemented as a 32-cycle iterative multiplier.

特性 Features

• Cortex-M4 Processor core
• Arm Cortex-M4 processor (version r0p1), running at frequencies of upto 204 MHz.
• Built-in Memory Protection Unit (MPU) supporting eight regions.
• Built-in Nested Vectored Interrupt Controller (NVIC).
• Hardware floating-point unit.
• Non-maskable Interrupt (NMI) input.
• JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints,and four watch points.
• Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB)support.
• System tick timer.
• Cortex-M0 Processor core
• Arm Cortex-M0 co-processor (version r0p0) capable of off-loading themain Arm Cortex-M4 application processor.
• Running at frequencies of up to 204 MHz.
• JTAG
• Built-in NVIC.
• Cortex-M0 subsystem
• Arm Cortex-M0 coprocessor controlling the SPI and SGPIO residing on aseparate AHB multilayer matrix. Includes 2 kB + 16 kB of SRAM.
• Running at frequencies of up to 204 MHz.
• Connected via a core-to-core bridge to the main AHB multilayer matrixand the main Arm Cortex-M4 processor.
• JTAG and built-in NVIC.
• On-chip memory
• Up to 1 MB on-chip dual bank flash memory with flash accelerator.
• 16 kB on-chip EEPROM data memory.
• 154 kB SRAM for code and data use.
• Multiple SRAM blocks with separate bus access. Two SRAM blocks can bepowered down individually.
• 64-bit of One-Time Programmable (OTP) memory for general-purposeuse.
• Two banks (256-bit total) of One-Time Programmable (OTP) memory forAES key storage. One bank can store an encrypted key for decodingthe boot image.
• AES engine for encryption and decryption of the boot image and data with DMAsupport and programmable via a ROM-based API.
• Configurable digital peripherals
• Serial GPIO (SGPIO) interface.
• SCTimer/PWM subsystem on AHB.
• Global Input Multiplexer Array (GIMA) allows to cross-connectmultiple inputs and outputs to event driven peripherals like thetimers, SCTimer/PWM, and ADC0/1.
• Serial interfaces
• Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB persecond.
• 10/100T Ethernet MAC with RMII and MII interfaces and DMA support forhigh throughput at low CPU load. Support for IEEE 1588 timestamping/advanced time stamping (IEEE 1588-2008 v2).
• One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY.
• One High-speed USB 2.0 Host/Device interface with DMA support,on-chip full-speed PHY and ULPI interface to external high-speedPHY.
• USB interface electrical test software included in ROM USB stack.
• One 550 UART with DMA support and full modem interface.
• Three 550 USARTs with DMA and synchronous mode support and a smartcard interface conforming to ISO7816 specification. One USART withIrDA interface.
• Up to two C_CAN 2.0B controllers with one channel each.
• Two SSP controllers with FIFO and multi-protocol support. Both SSPswith DMA support.
• One SPI controller.
• One Fast-mode Plus I²C-bus interface with monitor mode andwith open-drain I/O pins conforming to the full I²C-busspecification. Supports data rates of up to 1 Mbit/s.
• One standard I²C-bus interface with monitor mode and withstandard I/O pins.
• Two I²S interfaces, each with DMA support and with oneinput and one output.
• Digital peripherals
• External Memory Controller (EMC) supporting external SRAM, ROM, NORflash, and SDRAM devices.
• LCD controller with DMA support and a programmable display resolutionof up to 1024 H × 768 V. Supports monochrome and color STN panelsand TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table(CLUT) and 16/24-bit direct pixel mapping.
• Secure Digital Input Output (SD/MMC) card interface.
• Eight-channel General-Purpose DMA controller can access all memorieson the AHB and all DMA-capable AHB slaves.
• Up to 164 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors.
• GPIO registers are located on the AHB for fast access. GPIO portshave DMA support.
• Up to eight GPIO pins can be selected from all GPIO pins as edge andlevel sensitive interrupt sources.
• Two GPIO group interrupt modules enable an interrupt based on aprogrammable pattern of input states of a group of GPIO pins.
• Four general-purpose timer/counters with capture and matchcapabilities.
• One motor control Pulse Width Modulator (PWM) for three-phase motorcontrol.
• One Quadrature Encoder Interface (QEI).
• Repetitive Interrupt timer (RI timer).
• Windowed watchdog timer (WWDT).
• Ultra-low power Real-Time Clock (RTC) on separate power domain with256 bytes of battery powered backup registers.
• Alarm timer; can be battery powered.
• Analog peripherals
• One 10-bit DAC with DMA support and a data conversion rate of 400kSamples/s.
• Two 10-bit ADCs with DMA support and a data conversion rate of 400kSamples/s. Up to eight input channels per ADC.
• Unique ID for each device.
• Clock generation unit
• Crystal oscillator with an operating range of 1 MHz to 25 MHz.
• 12 MHz internal RC oscillator trimmed to 3 % accuracy overtemperature and voltage (1.5 % accuracy for Tamb = 0 °Cto 85 °C).
• Ultra-low power Real-Time Clock (RTC) crystal oscillator.
• Three PLLs allow CPU operation up to the maximum CPU rate without theneed for a high-frequency crystal. The second PLL can be used withthe High-speed USB, the third PLL can be used as audio PLL.
• Clock output.
• Power
• Single 3.3 V (2.4 V to 3.6 V) power supply with on-chip DC-to-DCconverter for the core supply and the RTC power domain.
• RTC power domain can be powered separately by a 3 V batterysupply.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down.
• Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals.
• Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery poweredblocks in the RTC power domain.
• Brownout detect with four separate thresholds for interrupt andforced reset.
• Power-On Reset (POR).
• Available as LQFP208, LBGA256, or TFBGA100 packages.

应用 Application

电机控制
电源管理
大型家电
RFID读卡器
嵌入式音频应用
工业自动化
电子计量