LPC4370FET100数据手册恩XP中文资料规格书

描述 Description

The LPC4370 are Arm Cortex-M4 based microcontrollers for embedded applicationswhich include an Arm Cortex-M0 coprocessor and an Arm Cortex-M0 subsystem formanaging peripherals, 282 kB of SRAM, advanced configurable peripherals such as theState Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface,two High-speed USB controllers, Ethernet, LCD, an external memory controller, andmultiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC4370operate at CPU frequencies of up to 204 MHz.
The Arm Cortex-M4 is a next generation 32-bit core that offers system enhancementssuch as low power consumption, enhanced debug features, and a high level of supportblock integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses aHarvard architecture with separate local instruction and data buses as well as a third busfor peripherals, and includes an internal prefetch unit that supports speculative branching.The Arm Cortex-M4 supports single-cycle digital signal processing and SIMDinstructions. A hardware floating-point processor is integrated in the core.
The LPC4370 include an application Arm Cortex-M0 coprocessor and a second Arm Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The Arm Cortex-M0 core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatiblewith the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with asimple instruction set and reduced code size.

特性 Features

• Main Cortex-M4 processor:
• Arm Cortex-M4 processor, running at frequencies of up to 204 MHz
• Arm Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions
• Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
• Hardware floating-point unit
• Non-maskable Interrupt (NMI) input
• JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints
• Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
• System tick timer
• Cortex-M0 coprocessor:
• Arm Cortex-M0 coprocessor capable of off-loading the main Arm Cortex-M4processor
• Running at frequencies of up to 204 MHz
• JTAG and built-in NVIC
• Cortex-M0 subsystem:
• Arm Cortex-M0 processor controlling the SPI and SGPIO peripherals residing ona separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM
• Running at frequencies of up to 204 MHz
• Connected via a core-to-core bridge to the main AHB multilayer matrix and themain Arm Cortex-M4 processor
• JTAG and built-in NVIC
• On-chip memory:
• 264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kBof SRAM on the Cortex-M0 subsystem
• Multiple SRAM blocks with separate bus access. Two SRAM blocks can bepowered down individually
• 64 kB ROM containing boot code and on-chip software drivers
• 64-bit + 256 bit general-purpose One-Time Programmable (OTP) memory
• Configurable digital peripherals:
• Serial GPIO (SGPIO) interface
• State Configurable Timer (SCT) subsystem on AHB
• Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like the timers, SCT, and ADC0/1
• Serial interfaces:
• Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second
• 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for highthroughput at low CPU load. Support for IEEE 1588 time stamping/advanced timestamping (IEEE 1588-2008 v2)
• One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY
• One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to external high-speed PHY
• USB interface electrical test software included in ROM USB stack
• One 550 UART with DMA support and full modem interface
• Three 550 USARTs with DMA and synchronous mode support and a smart cardinterface conforming to ISO7816 specification. One USART with IrDA interface
• Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge
• Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport
• One SPI controller
• One Fast-mode Plus I²C-bus interface with monitor mode and open-drain I/Opins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s
• One standard I²C-bus interface with monitor mode and with standard I/O pins
• Two I²S interfaces, each with DMA support and with one input and one output
• Digital peripherals:
• External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices
• LCD controller with DMA support and a programmable display resolution of up to1024 H x768 V. Supports monochrome and color STN panels and TFT colorpanels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixelmapping
• Secure Digital Input Output (SD/MMC) card interface
• Eight-channel General-Purpose DMA (GPDMA) controller can access all memorieson the AHB and all DMA-capable AHB slaves
• 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-downresistors and open-drain mode
• GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport
• Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources
• Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins
• Four general-purpose timer/counters with capture and match capabilities
• One motor control Pulse Width Modulator (PWM) for three-phase motor control
• One Quadrature Encoder Interface (QEI)
• Repetitive Interrupt timer (RI timer)
• Windowed watchdog timer (WWDT)
• Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers
• Alarm timer; can be battery powered
• Analog peripherals:
• One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.LBGA256 package only
• Two 8-channel, 10-bit ADCs (ADC0/1) with DMA support and a data conversionrate of 400 kSamples/s for a total of 16 independent channels. The 10-bit ADCsare only available on the LBGA256 package
• One 6-channel, 12-bit high-speed ADC (ADCHS) with DMA support and a dataconversion rate of 80 MSamples/s
• Unique ID for each device
• Clock generation unit:
• Crystal oscillator with an operating range of 1 MHz to 25 MHz
• 12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature andvoltage
• Ultra-low power Real-Time Clock (RTC) crystal oscillator
• Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL is dedicated to the High-speed USB, thethird PLL can be used as audio PLL
• Clock output
• Power:
• Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for thecore supply and the RTC power domain
• RTC power domain can be powered separately by a 3 V battery supply
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down
• Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals
• Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain
• Brownout detect with four separate thresholds for interrupt and forced reset
• Available as LBGA256 and TFBGA100 packages

应用 Application

电机控制
电源管理
大型家电
RFID读卡器
嵌入式音频应用
工业自动化
电子计量