LPC4337JET256数据手册恩XP中文资料规格书

描述 Description

The LPC435x/3x/2x/1x are Arm Cortex-M4 based microcontrollers for embeddedapplications which include an Arm Cortex-M0 coprocessor, up to 1 MB of flash and136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI),advanced configurable peripherals such as the State Configurable Timer (SCT) and theSerial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,LCD, an external memory controller, and multiple digital and analog peripherals. TheLPC435x/3x/2x/1x operate at CPU frequencies of up to 204 MHz.
The Arm Cortex-M4 is a next generation 32-bit core that offers system enhancementssuch as low power consumption, enhanced debug features, and a high level of supportblock integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses aHarvard architecture with separate local instruction and data buses as well as a third busfor peripherals, and includes an internal prefetch unit that supports speculative branching.The Arm Cortex-M4 supports single-cycle digital signal processing and SIMDinstructions. A hardware floating-point unit is integrated in the core.
The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core whichis upward code- and tool-compatible with the Cortex-M4 core. The Cortex-M0coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to204 MHz performance with a simple instruction set and reduced code size.

特性 Features

Cortex-M4 Processor coreArmCortex-M4 processor, running at frequencies of up to 204 MHz
Arm Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions
Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
Hardware floating-point unit
Non-maskable Interrupt (NMI) input
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support
System tick timer
Cortex-M0 Processor coreArm Cortex-M0 co-processor capable of off-loading the main Arm Cortex-M4application processor
Running at frequencies of up to 204 MHz
JTAG
Built-in NVIC
On-chip memoryUp to 1 MB on-chip dual bank flash memory with flash accelerator
16 kB on-chip EEPROM data memory
136 kB SRAM for code and data use
Multiple SRAM blocks with separate bus access. Two SRAM blocks can bepowered down individually
64 kB ROM containing boot code and on-chip software drivers
64 bit of general-purpose One-Time Programmable (OTP) memory
Configurable digital peripheralsSerial GPIO (SGPIO) interface
State Configurable Timer (SCT) subsystem on AHB
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like the timers, SCT, and ADC0/1
Serial interfacesQuad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for highthroughput at low CPU load. Support for IEEE 1588 time stamping/advanced timestamping (IEEE 1588-2008 v2)
One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY
One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to external high-speed PHY
USB interface electrical test software included in ROM USB stack
One 550 UART with DMA support and full modem interface
Three 550 USARTs with DMA and synchronous mode support and a smart cardinterface conforming to ISO7816 specification. One USART with IrDA interface
Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport
One SPI controller
One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/Opins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s
One standard I²C-bus interface with monitor mode and with standard I/O pins
Two I²S interfaces, each with DMA support and with one input and one output
Digital peripheralsExternal Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices
LCD controller with DMA support and a programmable display resolution of up to1024 H x 768 V. Supports monochrome and color STN panels and TFT colorpanels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixelmapping. Available on parts LPC4357/53 only
Secure Digital Input Output (SD/MMC) card interface
Eight-channel General-Purpose DMA controller can access all memories on theAHB and all DMA-capable AHB slaves
Up to 164 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors
GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport
Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources
Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins
Four general-purpose timer/counters with capture and match capabilities
One motor control Pulse Width Modulator (PWM) for three-phase motor control
One Quadrature Encoder Interface (QEI)
Repetitive Interrupt timer (RI timer)
Windowed watchdog timer (WWDT)
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers
Alarm timer; can be battery powered
Analog peripheralsOne 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.Up to eight input channels per ADC
Unique ID for each device
Clock generation unitCrystal oscillator with an operating range of 1 MHz to 25 MHz
12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature andvoltage (1 % accuracy for Tamb = 0 °C to 85 °C)
Ultra-low power Real-Time Clock (RTC) crystal oscillator
Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL can be used with the High-speed USB,the third PLL can be used as audio PLL
Clock output
PowerSingle 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for thecore supply and the RTC power domain
RTC power domain can be powered separately by a 3 V battery supply
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down
Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals
Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain
Brownout detect with four separate thresholds for interrupt and forced reset
Power-On Reset (POR)
Available as LQFP208, LQFP144, LBGA256, or TFBGA100 packages

应用 Application

电机控制
电源管理
白色家电
RFID读取器
嵌入式音频应用
工业自动化
电子计量