LMK04010中文资料具有 1185 至 1296MHz VCO 的低噪声抖动消除器：5 路输出用于 2VPEC/LVPEC数据手册TI规格书

描述 Description

The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

特性 Features

• Cascaded PLLatinum PLL Architecture
• Phase detector rate of up to 40 MHz
• Dual redundant input reference clock with LOS
• Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
• Input frequency-doubler
• Ultra-Low RMS Jitter Performance
• 200 fs RMS jitter (100 Hz – 20 MHz)
• Support clock rates up to 1080 MHz
• Five dedicated channel divider and delay blocks
• Industrial Temperature Range: -40 to 85 °C
• Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
• Data Converter Clocking
• Networking, SONET/SDH, DSLAM
• Military / Aerospace
• Video