LMK03000数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.

特性 Features

• Integrated VCO with Very Low Phase Noise Floor
• Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz
• VCO Divider Values of 2 to 8 (All Divides)
• Channel Divider Values of 1, 2 to 510 (even divides)
• LVDS and LVPECL Clock Outputs
• Partially Integrated Loop Filter
• Dedicated Divider and Delay Blocks on Each Clock Output
• Pin Compatible Family of Clocking Devices
• 3.15 to 3.45 V Operation
• Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
• 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a Clean Input Clock