ISPLSI5256VE数据手册Lattice中文资料规格书

描述 Description

ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.

特性 Features

• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
   — 3.3V Power Supply
   — User Selectable 3.3V/2.5V I/O
   — 12000 PLD Gates / 256 Macrocells
   — Up to 144 I/O Pins
   — 256 Registers
   — High-Speed Global Interconnect
   — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
   — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
   — PCB Efficient Ball Grid Array (BGA) Package Options
   — Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 165 MHz Maximum Operating Frequency
   — tpd = 6.0 ns Propagation Delay
   — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
   — Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality
   — Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
   — Enhanced Pin-Locking Architecture with Single Level Global Routing Pool and SuperWIDE GLBs
   — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
   — Macrocells Support Concurrent Combinatorial and Registered Functions
   — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
   — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
   — Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
   — Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell