ISPLSI2096E中文资料In-System Programmable SuperFAST High Density PLD数据手册Lattice规格书

描述 Description

The ispLSI 2096E is a High Density Programmable Logic Device. The device contains 96 Registers, 96 Universal I/O pins, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2096E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable systems.

特性 Features

• SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
   — 4000 PLD Gates
   — 96 I/O Pins, Six Dedicated Inputs
   — 96 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functional/JEDEC Upward Compatible with ispLSI 2096 Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 180 MHz Maximum Operating Frequency
   — tpd = 5.0 ns Propagation Delay
   — TTL Compatible Inputs and Outputs
   — 5V Programmable Logic Core
   — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
   — User-Selectable 3.3V or 5V I/O Supports MixedVoltage Systems
   — PCI Compatible Outputs
   — Open-Drain Output Option
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
   — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
   — Complete Programmable Device Can Combine Glue Logic and Structured Designs
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control to Minimize Switching Noise
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global Interconnectivity