ISPLSI2032VL数据手册Lattice中文资料规格书

描述 Description

The ispLSI 2032VL is a High Density Programmable Logic Device containing 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VL offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

特性 Features

• SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
   — 1000 PLD Gates
   — 32 I/O Pins, Two Dedicated Inputs
   — 32 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
   — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V and 2032VE Devices
• 2.5V LOW VOLTAGE 2032 ARCHITECTURE
   — Interfaces With Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant)
   — 45 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 180 MHz Maximum Operating Frequency
   — tpd = 5.0 ns Propagation Delay
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — 100% Tested at Time of Manufacture
   — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
   — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)
   — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic
   — Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   — Superior Quality of Results
   — Tightly Integrated with Leading CAE Vendor Tools
   — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™
   — PC and UNIX Platforms