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ISPLSI2064VL-100LB100中文资料莱迪思数据手册PDF规格书

ISPLSI2064VL-100LB100
厂商型号

ISPLSI2064VL-100LB100

功能描述

2.5V In-System Programmable SuperFAST??High Density PLD

文件大小

188.06 Kbytes

页面数量

14

生产厂商 Lattice Semiconductor
企业简称

LATTICE莱迪思

中文名称

莱迪思半导体公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-5 20:00:00

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ISPLSI2064VL-100LB100价格和库存,欢迎联系客服免费人工找货

ISPLSI2064VL-100LB100规格书详情

描述 Description

The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

特性 Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100 Functional, JEDEC and Pinout Compatible with

ispLSI 2064V and 2064VE Devices

• 2.5V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 3.3V TTL Devices (Inputs

and I/Os are 3.3V Tolerant)

— 60 mA Typical Active Current

• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 165MHz Maximum Operating Frequency

— tpd = 5.5ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-toMarket

and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

产品属性

  • 型号:

    ISPLSI2064VL-100LB100

  • 功能描述:

    CPLD - 复杂可编程逻辑器件 USE ispMACH 4000B

  • RoHS:

  • 制造商:

    Lattice

  • 存储类型:

    EEPROM

  • 大电池数量:

    128

  • 最大工作频率:

    333 MHz

  • 延迟时间:

    2.7 ns

  • 可编程输入/输出端数量:

    64

  • 工作电源电压:

    3.3 V

  • 最大工作温度:

    + 90 C

  • 最小工作温度:

    0 C

  • 封装/箱体:

    TQFP-100

供应商 型号 品牌 批号 封装 库存 备注 价格
LATTICE(莱迪思)
24+
TQFP-100(14x14)
1
优势代理渠道,原装正品,可全系列订货开增值税票
询价
LATTICE
0620+
QFP
260
一级代理,专注军工、汽车、医疗、工业、新能源、电力
询价
23+
原厂封装
9888
专做原装正品,假一罚百!
询价
LATTICE SEMICONDUCTOR
58
公司优势库存 热卖中!
询价
LATTICESEMIC
23+
65480
询价
LATTICE
24+
NA
2000
只做原装正品现货 欢迎来电查询15919825718
询价
Lattic
25+
25000
原厂原包 深圳现货 主打品牌 假一赔百 可开票!
询价
LATTICE(莱迪思)
24+
TQFP100(14x14)
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
LATTICE
23+
QFP
7000
询价
LATTICE
24+
QFP
21580
原装现货
询价