ISPLSI2064VE-135LT44I中文资料莱迪思数据手册PDF规格书

描述 Description

The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100 IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.

特性 Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100 Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices

• 3.3V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 280MHz* Maximum Operating Frequency

— tpd = 3.5ns* Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms