2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM

FEATURES • 1Mx36 and 2Mx18 configuration available. • On-chip Delay-Locked Loop (DLL) for wide data valid window. • Separate independent read and write ports with concurrent read and write operations. • Synchronous pipeline read with EARLY write operation. • Double Data Rate (DDR) interface f

文件：851.57 Kbytes 页数：29 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM

FEATURES • 1Mx36 and 2Mx18 configuration available. • On-chip Delay-Locked Loop (DLL) for wide data valid window. • Separate independent read and write ports with concurrent read and write operations. • Synchronous pipeline read with EARLY write operation. • Double Data Rate (DDR) interface f

文件：851.57 Kbytes 页数：29 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM

FEATURES • 1Mx36 and 2Mx18 configuration available. • On-chip Delay-Locked Loop (DLL) for wide data valid window. • Separate independent read and write ports with concurrent read and write operations. • Synchronous pipeline read with EARLY write operation. • Double Data Rate (DDR) interface f

文件：851.57 Kbytes 页数：29 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM

FEATURES • 1Mx36 and 2Mx18 configuration available. • On-chip Delay-Locked Loop (DLL) for wide data valid window. • Separate independent read and write ports with concurrent read and write operations. • Synchronous pipeline read with EARLY write operation. • Double Data Rate (DDR) interface f

文件：851.57 Kbytes 页数：29 Pages

ISSI

矽成半导体