8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

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文件：1.11874 Mbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

Package：66-TSSOP（szerokość 0，400"，10，16mm）；包装：管件 类别：集成电路（IC） 存储器 描述：IC DRAM 256MBIT PAR 66TSOP II

ISSI, Integrated Silicon Solution Inc

Package：66-TSSOP（szerokość 0，400"，10，16mm）；包装：管件 类别：集成电路（IC） 存储器 描述：IC DRAM 256MBIT PAR 66TSOP II

ISSI, Integrated Silicon Solution Inc

Package：66-TSSOP（szerokość 0，400"，10，16mm）；包装：托盘 类别：集成电路（IC） 存储器 描述：IC DRAM 256MBIT PAR 66TSOP II

ISSI, Integrated Silicon Solution Inc