NXP Semiconductors Document Number S32K1XX
Data Sheet: Advance Information Rev. 7， 04/2018
S32K1xx Data Sheet S32K1XX
Notes ? Power management
? Technical information for the S32K116 and_S32K118 – Low-power Arm Cortex-M4F/M0+ core with
device families is preliminary until these devices excellent energy efficiency
achieve qualification. – Power Management Controller (PMC) with multiple
power modes: HSRUN， RUN， STOP， VLPR， and_
? Following two are the available attachments with VLPS. Note: CSEc (Security) or EEPROM writes/
Datasheet: erase will trigger error flags in HSRUN mode (112
– S32K1xx_Orderable_Part_Number_ List.xlsx MHz) because this use case is not allowed to
– S32K1xx_Power_Modes_Configuration.xlsx execute simultaneously. The device will need to
Key Features switch to RUN mode (80 Mhz) to execute CSEc
(Security) or EEPROM writes/erase.
? Operating characteristics – Clock gating and_low power operation supported on
– Voltage range: 2.7 V to 5.5 V specific peripherals.
– Ambient temperature range: -40 °C to 105 °C for ? Memory and_memory interfaces
HSRUN mode， -40 °C to 125 °C for RUN mode – Up to 2 MB program flash memory with ECC
? Arm? Cortex-M4F/M0+ core， 32-bit CPU – 64 KB FlexNVM for data flash memory with ECC
– Supports up to 112 MHz frequency (HSRUN mode) and_EEPROM emulation. Note: CSEc (Security) or
with 1.25 Dhrystone MIPS per MHz EEPROM writes/erase will trigger error flags in
