IDT72V215L15TF~1.jpg
IDT72V215L15TF.jpg
FEATURES:• 256 x 18-bit organization array (IDT72V205)• 512 x 18-bit organization array (IDT72V215)• 1,024 x 18-bit organization array (IDT72V225)• 2,048 x 18-bit organization array (IDT72V235)• 4,096 x 18-bit organization array (IDT72V245)• 10 ns read/write cycle time• 5V input tolerant• IDT Standard or First Word Fall Through timing• Single or double register-buffered Empty and Full flags• Easily expandable in depth and width• Asynchronous or coincident Read and Write Clocks• Asynchronous or synchronous programmable Almost-Emptyand Almost-Full flags with default settings• Half-Full flag capability• Output enable puts output data bus in high-impedanc state• High-performance submicron CMOS technology• Available in a 64-lead thin quad flatpack (TQFP/STQFP)• Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:The IDT72V205/72V215/72V225/72V235/72V245 are functionally compatibleversions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,designed to run off a 3.3V supply for exceptionally low power consumption.These devices are very high-speed, low-power First-In, First-Out (FIFO)memories with clocked read and write controls. These FIFOs are applicablefor a wide variety of data buffering needs, such as optical disk controllers, LocalArea Networks (LANs), and interprocessor communication.These FIFOs have 18-bit input and output ports. The input port is controlledby a free-running clock (WCLK), and an input enable pin (WEN). Data is readinto the synchronous FIFO on every clock when WEN is asserted. The outputport is controlled by another clock pin (RCLK) and another enable pin (REN).The Read Clock(RCLK) can be tied to the Write Clock for single clock operationor the two clocks can run asynchronous of one another for dual-clock operation.An Output Enable pin (OE) is provided on the read port for three-state controlof the output.The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the program-mable flags is controlled by a simple state machine, and is initiated by assertingthe Load pin (LD). A Half-Full flag (HF) is available when the FIFO is usedin a single device configuration.There are two possible timing modes of operation with these devices: IDTStandard mode and First Word Fall-Through (FWFT) mode.In IDT Standard Mode, the first word written to an empty FIFO will not appearon the data output lines unless a specific read operation is performed. A readoperation, which consists of activating REN and enabling a rising RCLK edge,will shift the word from internal memory to the data output lines.In FWFT mode, the first word written to an empty FIFO is clocked directlyto the data output lines after three transitions of the RCLK signal. A REN doesnot have to be asserted for accessing the first word.These devices are depth expandable using a Daisy-Chain technique orFirst Word Fall Through mode (FWFT). The XI and XO pins are used to expandthe FIFOs. In depth expansion configuration, First Load (FL) is grounded onthe first device and set to HIGH for all other devices in the Daisy Chain.The IDT72V205/72V215/72V225/72V235/72V245 are fabricated usingIDT’s high-speed submicron CMOS technology.
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