Overview
The MPC5200B integrates a high performance
MPC603e series e300 core with a rich set of peripheral
functions focused on communications and systems
integration. The e300 core design is based on the
PowerPC® core architecture. MPC5200B incorporates
an innovative BestComm I/O subsystem, which isolates
routine maintenance of peripheral functions from the
embedded e300 core. The MPC5200B contains a
SDRAM/DDR Memory Controller, a flexible External
Bus Interface, PCI Controller, USB, ATA, Ethernet, six
Programmable Serial Controllers (PSC), I2
C, SPI, CAN, J1850, Timers, and GPIOs.
Features
Key features are shown below.
• MPC603e series e300 core
— Superscalar architecture
— 760 MIPS at 400 MHz (-40 to +85 o
C)
— 16 k Instruction cache, 16 k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard and Critical interrupt capability
• SDRAM / DDR Memory Interface
— up to 133-MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per CS, two CS available
— 32-bit data bus
— Built-in initialization and refresh
• Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit databus with up to 25-bit address
• Peripheral Component Interconnect (PCI) Controller
— Version 2.2 PCI compatibility
— PCI initiator and target operation
— 32-bit PCI Address/Data bus
— 33- and 66-MHz operation
— PCI arbitration function
• ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
• BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16 kBytes)
• 6 Programmable Serial Controllers (PSC), configurable for the following:
— UART or RS232 interface
— CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97
— Full duplex SPI mode
— IrDA mode from 2400 bps to 4 Mbps
• Fast Ethernet Controller (FEC)
— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface
• Universal Serial Bus Controller (USB)
— USB Revision 1.1 Host
— Open Host Controller Interface (OHCI)
— Integrated USB Hub, with two ports.
• Two Inter-Integrated Circuit Interfaces (I2
C)
• Serial Peripheral Interface (SPI)
• Dual CAN 2.0 A/B Controller (MSCAN)
— Motorola Scalable Controller Area Network (MSCAN) architecture
— Implementation of version 2.0A/B CAN protocol
— Standard and extended data frames
• J1850 Byte Data Link Controller (BDLC)
— J1850 Class B data communication network interface compatible and ISO compatible for low
speed (<125 kbps) serial data communications in automotive applications.
— Supports 4X mode, 41.6 kbps
— In-frame response (IFR) types 0, 1, 2, and 3 supported
• Systems level features
— Interrupt Controller supports four external interrupt request lines and 47 internal interrupt
sources
— GPIO/Timer functions
– Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a
variety of interrupt/WakeUp capabilities.
– Eight GPIO pins with timer capability supporting input capture, output compare, and pulse
width modulation (PWM) functions
— Real-time Clock with one-second resolution
— Systems Protection (watch dog timer, bus monitor)
— Individual control of functional block clock sources
— Power management: Nap, Doze, Sleep, Deep Sleep modes
— Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
• Test/Debug features
— JTAG (IEEE 1149.1 test access port)
— Common On-chip Processor (COP) debug port
• On-board PLL and clock generation
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