3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Description The Z9972 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations.

文件：87.59 Kbytes 页数：9 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Infineon

英飞凌

3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Description The Z9972 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations.

文件：87.59 Kbytes 页数：9 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Description The Z9972 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations.

文件：87.59 Kbytes 页数：9 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司