ICSSSTUAF32866BHLFT中文资料IDT数据手册PDF规格书

描述 Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low.

特性 Features

• 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality

• Supports SSTL_18 JEDEC specification on data inputs and outputs

• Supports LVCMOS switching levels on C0, C1, and RESET inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 96-ball LFBGA package

Applications

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 667 and 800