Package：28-SSOP（0.209"，5.30mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK BUF DDR 200MHZ 1CIRC

Renesas Electronics America Inc

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 页数：6 Pages

ICST

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Description Output Features DDR Zero Delay Clock Buffer • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Key Specifications • PEAK - PEAK jitt

文件：240.76 Kbytes 页数：8 Pages

RENESAS

瑞萨

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 页数：6 Pages

ICST