Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 页数：6 Pages

ICST

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Description Output Features DDR Zero Delay Clock Buffer • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Key Specifications • PEAK - PEAK jitt

文件：240.76 Kbytes 页数：8 Pages

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瑞萨

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz):

文件：54.59 Kbytes 页数：6 Pages

ICST

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ICS

上传：深圳市亚泰盈科电子有限公司

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ICS

上传：深圳市得捷芯城科技有限公司