ICS650R-12T集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS650-12 is a low cost, low jitter, high performance clock synthesizer designed to produce fixed clock outputs of 13.5 MHz and 27.0 MHz and four selectable clock outputs of two Processor Clocks (PCLK1 and PCLK2), Audio Clock (ACLK), and Communications Clock (CCLK). Using our patented analog PhaseLocked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal input to produce clocks ideal for Digital Video/MPEG based applications.

特性 Features

• Packaged in 20 pin tiny SSOP (QSOP)

• Input Frequency of 27.0 MHz

• Zero ppm synthesis error in output clocks

• Provides fixed 13.5 MHz and 27.0 MHz. Also provides two selectable Processor Clocks, one Audio Clock, and one Communications Clock

• Ideal for Digital Video/MPEG-based applications

• 3.3 V or 5.0 V operating voltage

• Entire chip powers down (when CS1=CS0=0)