ICS650R-07集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS650-07B is a low cost, low jitter, high performance clock synthesizer customized for Broadcom. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks of 25.0 MHz, two 125.0 MHz, 133.33 MHz, and a selectable 33.3/66.6 MHz clock. All output clocks are frequency locked together. The ICS650-07B outputs all have 0 ppm synthesis error.

特性 Features

• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)

• 25.00 MHz fundamental crystal or clock input

• Four fixed output clocks of 25 MHz, 133.33 MHz, and two copies of 125 MHz

• One selectable output clock of 33.3 or 66.6 MHz

• Zero ppm synthesis error in all clocks

• PCI clock switching occurs within 1 µs

• Ideal for Broadcom’s BCM5600 chipset

• Full CMOS output swing

• Advanced, low power, sub-micron CMOS process

• 3.0 V to 5.5 V operating voltage