ICS650R-01I集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS650-01 is a low cost, low jitter, high performance clock synthesizer for system peripheral applications. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 14.31818 MHz crystal input to produce up to eight output clocks.

特性 Features

• Packaged in 20 pin tiny SSOP (QSOP)

• Operating VDD of 3.3V or 5V

• Less than one ppm synthesis error in all clocks

• Inexpensive 14.31818 MHz crystal or clock input

• Provides Ethernet and Fast Ethernet clocks

• Provides SCSI clocks

• Provides PCI clocks

• Selectable AC97 audio clock

• Selectable USB clock

• OE pin tri-states the outputs for testing

• Selectable frequencies on three clocks

• Duty cycle of 40/60

• Advanced, low power CMOS process