ICS548A-03中文资料IDT数据手册PDF规格书

描述 Description

The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two. Using our patented Phase-Locked Loop (PLL) techniques, the device operates from a frequency range of 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode.

In applications that need to maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) modes should be used.

This chip is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers.

特性 Features

• Packaged in 16-pin SOIC (150 mil)

• Input clock up to 160 MHz in the non-PLL mode

• Provides clock outputs of CLK, CLK, and CLK/2

• Low skew (500 ps) on CLK, CLK, and CLK/2

• All outputs can be tri-stated

• Entire chip can be powered down by changing one or two select pins

• 3.3 V operating range

• Available in commercial and industrial temperature ranges

• RoHS 5 (green) or RoHS 6 (green and lead free) compliant package