ICS548-03中文资料ICST数据手册PDF规格书

描述 Description

The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using our patented analog Phase-Locked Loop (PLL) techniques, the device operates from a frequency range from 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode.

特性 Features

• Packaged in 16 pin narrow (150 mil) SOIC

• Input clock up to 160 MHz in the non-PLL mode

• Provides clock outputs of CLK, CLK, and CLK/2

• Low skew (500 ps) on CLK, CLK, and CLK/2

• All outputs can be tri-stated

• Entire chip can be powered down by changing one or two select pins

• 3.3V or 5.0V operating voltage