CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features • Packaged as 28-pin SSOP, Pb-free (150 mil body) • Synchronizes fractional clocks rising edges • PECL IN to CMOS OUT • Pin selectable dividers • Zero input to output skew • User determines the output frequency—no software needed • Slices frequency or period • Input clock frequen

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Clock Slicer User Configurable PECL Input Zero Delay Buffer

Description The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer mul

文件：162.16 Kbytes 页数：8 Pages

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Clock Slicer User Configurable PECL Input Zero Delay Buffer

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瑞萨

ICS
TSSOP20

ICS

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IDT
SOP-8

IDT

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