HY57V161610ETP-5I数据手册SK hynix中文资料规格书

描述 Description

DESCRIPTION
THE Hynix HY57V161610E is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610E is organized as 2banks of 524,288x16. HY57V161610E is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.FEATURES
• Single 3.0V to 3.6V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by UDQM/LDQM
• Internal two banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
   - 1, 2, 4, 8 and Full Page for Sequence Burst
   - 1, 2, 4 and 8 for Interleave Burst

特性 Features

• Single 3.0V to 3.6V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of system clock
• Data mask function by UDQM/LDQM
• Internal two banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
   - 1, 2, 4, 8 and Full Page for Sequence Burst
   - 1, 2, 4 and 8 for Interleave Burst