HEF4035BN中文资料PDF规格书
HEF4035BN规格书详情
DESCRIPTION
The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions (O0 to O3), a true/complement input (T/C) and an overriding asynchronous master reset input (MR). Each register is of a D-type master-slave flip-flop.
Operation is synchronous (except for MR) and is edge-triggered on the LOW to HIGH transition of the CP input. When PE is HIGH, data is loaded into the register from P0 to P3 on the LOW to HIGH transition of CP.
When PE is LOW, data is shifted into the first register position from J and K and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. D-type entry is obtained by interconnecting J and K. When J = HIGH and K = LOW the first stage is in the toggle mode. When J = LOW and K = HIGH the first stage is in the hold mode.
产品属性
- 型号:
HEF4035BN
- 制造商:
PHILIPS
- 制造商全称:
NXP Semiconductors
- 功能描述:
4-bit universal shift register
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NXP/恩智浦 |
22+ |
DIP |
60 |
原装现货假一赔十 |
询价 | ||
PHILIPS |
21+ |
DIP-20 |
30 |
原装现货假一赔十 |
询价 | ||
NXP/恩智浦 |
23+ |
SOP-16 |
90000 |
只做原装 全系列供应 价格优势 可开增票 |
询价 | ||
NXP |
21+ |
35200 |
一级代理/放心采购 |
询价 | |||
PHILIPS/飞利浦 |
22+ |
DIP-20 |
5623 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
PHILIPS |
22+ |
CDIP |
8000 |
原装正品支持实单 |
询价 | ||
NXP/恩智浦 |
23+ |
NA/ |
3293 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
PHI |
22+ |
DIP |
2987 |
只售原装自家现货!诚信经营!欢迎来电! |
询价 | ||
PHI |
96+ |
DIP20 |
8 |
询价 | |||
PHILIPS/飞利浦 |
QQ咨询 |
CDIP |
828 |
全新原装 研究所指定供货商 |
询价 |