4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR

文件：91.7 Kbytes 页数：8 Pages

PHI

PHI

4-stage divide-by-8 Johnson counter

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