4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 页数：10 Pages

PHI

PHI

1SCHOTTKY MIXER DIODE

DESCRIPTION: The ASI MA40160 s a Silicon medium barrier Schottky Diode Designed for normal L.O. drive, Mixer Applications up to 26 GHz. FEATURES: • Ceramic Package

文件：15.94 Kbytes 页数：1 Pages

ASI

C2MOS DIGITAL INTERGRATED CIRCUIT SILICON MONOLITHIC

文件：296.14 Kbytes 页数：8 Pages

TOSHIBA

东芝

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 页数：10 Pages

PHI

PHI

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 页数：10 Pages

PHI

PHI

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

文件：155.57 Kbytes 页数：10 Pages

PHI

PHI