HEF40160BT中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count enable trickle (CET)), buffered outputs from all four bit positions (O0to O3) and a terminal count output (TC).