HD74HC78FPEL技术资料参数供应价格瑞萨-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
HD74HC78FPEL	文件：105.89 Kbytes Page：7 Pages	Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and changestate on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are ind 文件：105.89 Kbytes 页数：7 Pages	RENESAS 瑞萨	RENESAS
HD74HC78FPEL	文件：124.65 Kbytes Page：9 Pages	Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) 文件：124.65 Kbytes 页数：9 Pages	RENESAS 瑞萨	RENESAS
HD74HC78RPEL	文件：124.65 Kbytes Page：9 Pages	Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) 文件：124.65 Kbytes 页数：9 Pages	RENESAS 瑞萨	RENESAS
HD74HC78RPEL	文件：105.89 Kbytes Page：7 Pages	Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and changestate on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are ind 文件：105.89 Kbytes 页数：7 Pages	RENESAS 瑞萨	RENESAS

更多HD74HC78FPEL供应商更新时间2025-10-6 16:30:00