HD74HC78FPEL中文资料瑞萨数据手册PDF规格书

Description

This flip-flop is edge sensitive to the clock input and changestate on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are independent ofthe clock and accomplished by a low logic level on the corresponding input.

Features

• High Speed Operation: tpd(Clock to Q) = 20 ns typ (CL= 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC= 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC(static) = 2 µA max (Ta = 25°C)