Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

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HitachiHitachi Semiconductor

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Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

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Octal D-type Flip-Flops (with Enable)

Description\nInformation at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the pos •  High Speed Operation: tpd= 13 ns typ (CL= 50 pF)\n•  High Output Current: Fanout of 10 LSTTL Loads\n•  Wide Operating Voltage: VCC= 2 to 6 V\n•  Low Input Current: 1 µA max\n•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C);

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Standard IC>General-Purpose Logics>HD74HC Series

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Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨

Octal D-type Flip-Flops (with Enable)

Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the

文件：99.38 Kbytes 页数：7 Pages

RENESAS

瑞萨